This invention relates to the field of processor architectures, particularly to methods of exception handling.
Maintaining a precise exception handling model in processors is increasingly difficult as processor designs implement deeper pipelines and out of order executions in increasingly higher performance processor designs. The Load/Store Unit (LSU) centric instruction commit is built around the LSU's special needs. Typically, the LSU is not able to determine its exceptions until the end of the D stage when it has almost completed its execution. For store instructions, the LSU needs to know that the store has completed before it executes the store and modifies the cache.
A typical load/store unit instruction is committed at a late processor architecture pipeline stage. There is therefore a corresponding increasing need to simplify exception processing to gain back higher performance exception handling processing in the more complicated deeper pipelines of out of order executions.